1. Field of the Invention
The present invention relates to a sum-of-products arithmetic unit. More specifically, the present invention relates to a sum-of-products arithmetic unit which functions as an IIR (Infinite Impulse Response) filter (recursive filter) or FIR (Finite Impulse Response) filter (non-recursive filter) and achieves a high transfer rate.
2. Description of the Related Art
In recent years, requirements of filtering data by the use of digital filters have been increasing in the fields of automobile, mechatronics, etc. Sum-of-product arithmetic units, DSPs (Digital Signal Processors) which are LSIs (Large-Scale Integrated Circuits) dedicated to digital signal processing, and so on have been put to practical use. In these fields, filtering computations are mainly used in which a small number of operation terms is involved, and IIR filters with high processing speeds are often used.
FIG. 1 shows an arrangement of a conventional sum-of-products arithmetic unit using FIR.
This arithmetic unit comprises two registers that can each be implemented by a random access memory (RAM), i.e., a coefficient register 800 and a data register 810, a multiplier 830 which multiplies outputs of registers 800 and 810 together, an adder 840 which takes the output of multiplier 830 as its input, an intermediate data register 850 which stores the intermediate result of the sum-of-products operation performed by multiplier 830 and adder 840, a result register 860 which stores the result of an arithmetic operation of sum-of-products, and an address decoder 870 which specifies addresses of data register 810. Adder 840 takes the output of intermediate data register 850 as its other input, thereby enabling a sum-of-products arithmetic operation.
In operation, first, coefficient data and input data are transferred to coefficient register 800 and data register 810, respectively, over a data bus 820. For example, for a sum of products for four terms, four pieces of input data and four pieces of coefficient data are entered into data register 810 and coefficient register 800, respectively. One input and one coefficient are multiplied in turn and the resulting products are then added, thereby performing FIR filtering computation. In writing data into data register 810, its addresses are specified by an external CPU not shown. That is, an address is loaded into address decoder 870 from the external CPU, then decoded by it to obtain a real address of the data register. A piece of input data is written into that address via data bus 820, and the input data is read from that address, then entered into multiplier 830, starting a sum-of-products operation.
In order to implement an IIR filter by this arithmetic unit, it is required to transfer the result of a sum-of-products operation stored in result register 860 to data register 810 over data bus 820 and start another sum-of-products operation again. That is, it is required for the external CPU to address data register 810 to write the contents of result register 860 into its real address obtained by address decoder 870, then specify a read address of the data register and start the next sum-of-products operation.
With the conventional method, however, the external CPU must direct data register addressing and the start of sum-of-products operations. Thus, software is needed for this control and the speed of processing such as data transfer becomes low.
In addition, since the CPU specifies write addresses in the data register, an address storage area in the CPU is needed for each piece of data.